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mc141803 3C313 motorola lcd segment / common driver with controller cmos mc141803 is a cmos lcd driver which consists of 4 annunciator outputs and 153 high voltage lcd driving signals (33 commons and 120 segments). mc141803 is split common output design. it has parallel interface capability for operating with general mcu. besides the general lcd driver features, it has an on chip lcd bias voltage generator circuit such that fewer external com- ponents are required during application. ? single supply operation, 2.4 v - 3.5 v ? operating temperature range : -30 to 85 c ? low current stand-by mode (<500na) ? on chip bias voltage generator ? 8 bit parallel interface ? graphic mode operation ? on chip 120 x 33 graphic display data ram ? 120 segment drivers, 33 common drivers ? selectable 1/16, 1/32, 1/33 multiplex ratio ? selectable on chip voltage doubler and tripler ? selectable 1:5 or 1:7 bias ratio ? re-mapping of row and column drivers ? four stand alone annunciator (static icon) driver circuits ? low power icon mode driven by com32 in special driving scheme ? selectable lcd driving voltage temperature coefficients ? 16 level internal contrast control ? external contrast control provided ? master clear ram ? standard tab package ordering information MC141803T tab tab MC141803T rev 4 2/98 mc141803 motorola semiconductor technical data
motorola 3C314 mc141803 lcd driving voltage generator tripler, doubler, voltage regulator, voltage divider, contrast control, temperature compensation bp annun0 to annun3 com0 to com32 seg0~seg119 annunciator control circuit osc1 osc2 dvss dvdd res ce r/w d0~d7 vll6 vll2 vcc vr vf c2p c2n c1p c1n dum2 dum1 c+ c- avdd avss gddram 33 x 120 bits command decoder parallel interface command interface display timing generator 120 bit latch 33 bit latch hv buffer cell level shifter level selector cs (clk) d/c block diagram
mc141803 3C315 motorola MC141803T pin assignment (copper view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 dummy dummy dummy dummy dvss osc1 avss vr vf vcc c- c+ dum2 osc2 dum1 vll6 vll5 vll4 vll3 vll2 c2n c2p c1n c1p avdd dvss ce d7 d6 d5 d4 d3 d2 d1 d0 dvss cs(clk) r/w d/c dvss res dvdd com32 com0 com1 com2 com3 com4 . . . . . com12 com13 com14 com15 seg0 seg1 seg2 seg3 seg4 . . . . . . . . . . . . seg117 seg118 seg119 com32 com31 com30 com29 com28 . . . . com19 com18 com17 com16 annun0 annun1 annun2 annun3 bp 197 196 195 194 193 192 . . . . . 184 183 182 181 180 179 178 177 176 . . . . . . . . . . . 63 62 61 60 59 58 57 56 . . . . 47 46 45 44 43 42 41 40 39
motorola 3C316 mc141803 maximum ratings* (voltages referenced to v ss , t a =25?c) symbol parameter value unit av dd ,dv dd supply voltage -0.3 to +4.0 v v cc v ss -0.3 to v ss +10.5 v v in input voltage v ss -0.3 to v dd +0.3 v i current drain per pin excluding v dd and v ss 25 ma t a operating temperature -30 to +85 ?c t stg storage temperature range -65 to +150 ?c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin descrip- tion section. v ss = av ss = dv ss (dv ss = v ss of digital circuit, av ss = v ss of analogue circuit) v dd = av dd = dv dd (dv dd = v dd of digital circuit, av dd = v dd of analogue circuit) this device contains circuitry to protect the inputs against damage due to high static voltages or elec- tric ?elds; however, it is advised that normal precau- tions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recom- mended that v in and v out be constrained to the range v ss < or = (v in or v out ) < or = v dd . reliability of operation is enhanced if unused input are con- nected to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. this device may be light sensitive. caution should be taken to avoid exposure of this device to any light source during normal operation. this device is not radiation protected. electrical characteristics (voltage referenced to v ss , t a =25?c) symbol parameter test condition min typ max unit v dd supply voltage (absolute value referenced to v ss )av dd =dv dd 2.4 3.15 3.5 v i ac i dp1 i dp2 i sb1 i sb2 i sb3 i icon supply current (measure with v dd ?xed at 3.15v) access mode supply current drain from pin avdd and dvdd. display mode supply current drain from pin avdd and dvdd. display mode supply current drain from pin avdd and dvdd stand-by mode supply current drain from pin avdd and dvdd stand-by mode supply current drain from pin avdd and dvdd. stand-by mode supply current drain from pin avdd and dvdd. stand-by mode supply current drain from pin avdd and dvdd internal dc/dc converter on, display on, tripler enable, r/w accessing, t cyc =1mhz, osc. freq.=50khz, 1/33 duty cycle,1/7 bias. internal dc/dc converter on, display on, tripler enable, r/w halt, osc. freq.=50khz, 1/33 duty cycle,1/7 bias. internal dc/dc converter on, display on, tripler enable, r/w halt, osc. freq.=38.4khz, 1/33 duty cycle,1/7 bias. display off, oscillator disabled, r/w halt display off, oscillator enable, r/w halt, external oscillator and frequency = 50khz. display off, oscillator enable, r/w halt, internal oscillator and frequency = 50khz. low power icon mode, oscillator enable, r/w halt, internal oscillator and frequency = 50khz 0 0 0 0 0 0 - 200 80 60 300 2.5 5 15 300 150 100 500 5 10 25 m a m a m a na m a m a m a v cc1 v cc2 v lcd vlcd voltage (absolute value referenced to v ss ) lcd driving voltage generator output voltage at pin v cc . lcd driving voltage generator output voltage at pin v cc . lcd driving voltage input at pin v cc . display on, internal dc/dc converter enabled, tripler enable, osc. freq. = 50khz, regulator enabled, divider enabled iout <= 100 m a display on, internal dc/dc converter enabled, doubler enable, osc. freq. = 50khz, regulator enabled, divider enabled iout <= 100 m a internal dc/dc converter disabled. - - 5 3*dv dd 2*dv dd - 10.5 7 10.5 v v v v oh1 v ol1 v r1 v r2 output voltage output high voltage at pins d0-d7, annun0-3, bp and osc2. output low voltage at pins d0-d7, annun0-3, bp and osc2. lcd driving voltage source at pin vr lcd driving voltage source at pin vr i out =100 m a i out =100 m a regulator enabled, i out =50 m a regulator disabled 0.8*v dd 0 0 - - - - floating v dd 0.2*v dd v cc - v v v v v ih1 v il1 input voltage input high voltage at pins res , ce, cs , d0-d7, r/w , d/c , osc1 and osc2. input low voltage at pins res , ce, cs , d0-d7, r/ w , d/c , osc1 and osc2. 0.8*v dd 0 - - v dd 0.2*v dd v v
mc141803 3C317 motorola electrical characteristics (voltage referenced to v ss , dv dd =2.4-3.15v, t a =25?c) * the formula for the temperature coefficient is: symbol parameter test condition min typ max unit v ll6 v ll5 v ll4 v ll3 v ll2 lcd display voltage. (lcd driving voltage output from pins vll6, vll5, vll4, vll3 and vll2.) 1/5 bias ratio, voltage divider enabled, regula- tor enabled. - - - - - v r 0.8*v r 0.6*v r 0.4*v r 0.2*v r - - - - - v v v v v v ll6 v ll5 v ll4 dum2 dum1 v ll3 v ll2 1/7 bias ratio, internal voltage divider enabled, regulator enabled - - - - - - - v r 6/7*v r 5/7*v r 4/7*v r 3/7*v r 2/7*v r 1/7*v r - - - - - - - v v v v v v v v ll6 v ll5 v ll4 v ll3 v ll2 external voltage generator, internal voltage divider disable 0.5v cc 0.5v cc 0.5v cc v ss v ss - - - - - v cc v cc v cc 0.5v cc 0.5v cc v v v v v i oh i ol i oz output current output high current source from pins d0-d7, annun0-3, bp and osc2 output low current drain by pins d0-d7, annun0-3, bp and osc2 output tri-state current drain source at pins d0- d7 and osc2 v out =v dd -0.4v. v out =0.4v. 100 - -1 - - - - -100 1 m a m a m a i il /i ih input current at pins res , ce, cs , d0-d7, r/w , d/c osc1 and osc2. -1 - 1 m a ron on resistance channel resistance between lcd driving signal pins (seg and com) and driving voltage input pins (v ll2 to v ll6 ). during display on, 0.1v apply between two ter- minals, v cc within operating voltage range. - - 10 k w v sb memory retention voltage (dv dd ) standby mode, retained all internal con?guration and ram data 1.8 - - v c in input capacitance all control pins - 5 7.5 pf ptc0 ptc1 ptc2 ptc3 temperature coef?cient compensation flat temperature coef?cient temperature coef?cient 1* temperature coef?cient 2* temperature coef?cient 3* tc1=0, tc2=0, voltage regulator disabled. tc1=0, tc2=1, voltage regulator enabled. tc1=1, tc2=0, voltage regulator enabled. tc1=1, tc2=1, voltage regulator enabled. - - - - 0.0 -0.18 -0.22 -0.35 - - - - % % % % v cn internal contrast control vr output voltage with internal contrast control selected. 16 voltage levels controlled by soft- ware. each level is typical of 2.25% of the regu- lator output voltage. internal regulator enabled, internal contrast control enabled. - 18 - % tc(%)= vr at 50?c - vr at 0?c 50?c - 0?c x 1 vr at 25?c x100%
motorola 3C318 mc141803 electrical characteristics (voltage referenced to v ss , av dd =dv dd =2.4 to 3.5v, t a =25?c) total variation of vr d v rt is affected by the following factors : process variation of regulator d v r external v dd variation contributed to regulator d v vdd external resistor pair ra/rf contributed to regulator d v res where assume external v dd variation is 6% at 3.15v and 1% variation resistor used at application tc level d v vdd (%) d v r (%) d v res (%) d v rt (%) reference generator tc0 tc1 tc2 tc3 6.0 4.0 2.5 1.4 2.5 1.414 6.652 4.924 3.805 3.195 v rt d v d r () 2 v v dd d () 2 v res d () 2 ++ = ac electrical characteristics (t a =25?c, voltage referenced to v ss , v dd =2.4 to 3.15v) set clock frequency to slow : f frm1 =f osc1 /576 set clock frequency to normal : f frm2 =f osc2 /768 symbol parameter test condition min typ max unit f osc1 f ann1 f frm1 f con1 oscillation frequency. oscillation frequency of display timing generator with 60hz frame frequency. annunciator display (50% duty cycle) from pins annun0-3 and bp lcd driving signal frame frequency. lcd driving signal frame frequency. set clock frequency to slow either external clock input or internal oscillator enable, either 1/32 or 1/16 duty cycle, graphic display mode. either external clock input or internal oscillator enable, 1/33 duty cycle, graphic display mode. - - - - 38.4 18.75 66 64 - - - - khz hz hz hz fosc 2 f ann2 f frm2 f con2 oscillation freq. oscillation frequency of display timing generator with 60hz frame frequency. annunciator display frequency (with 50% duty cycle) from pins annun0-3 and bp lcd driving signal frame frequency. lcd driving signal frame frequency. set clock frequency to normal either external clock input or internal oscillator enable, either 1/32 or 1/16 duty cycle. either external clock input or internal oscillator enable, 1/33 duty cycle. - - - - 50 24.4 65 63 - - - - khz hz hz hz osc internal oscillation frequency internal osc oscillation frequency with different value of feedback resistor. internal oscillator enabled. v dd within operation range. see figure 1 for the relationship
mc141803 3C319 motorola 100k 500k 1.0m 1.5m 2.0m resistor value between osc1 and osc2 ( w ) oscillation frequency (hz) 200k 90k 70k 50k 30k 10k 220k figure 1. internal oscillator frequency relationship with external resistor value ac operation conditions and charateristics electrical characteristics lcd panel driving signal timing (t a =-30 to 85?c, v dd = 2.4 to 3.5v, v ss = 0v) figure 2. lcd driving signal timing diagram 1234 1234 vll6 vll5 vll4 vll3 vll2 vll1 vll6 vll5 vll4 vll3 vll2 vll1 comx segy 1/f ann bp, annun0-3
motorola 3C320 mc141803 valid data t cycle t eh t as t ah t dh t ds cs r/w d/c d0-d7 ce table 2a. parallel timing characteristics (write cycle) (t a =-30 to 85?c, dv dd =2.4 to 3.5v, v ss =0v) symbol parameter min typ max unit t cycle enable cycle time 600 - - ns t eh enable pulse width 290 - - ns t as address setup time 5 - - ns t ds data setup time 290 - - ns t dh data hold time 20 - - ns t ah address hold time 20 - - ns figure 3. timing characteristics (write cycle)
mc141803 3C321 motorola valid data t cycle t eh t as t ah t dh t ds cs r/w d/c d0-d7 ce table 2b. parallel timing characteristics (read cycle) (t a =-30 to 85?c, dv dd =2.4 to 3.5v, v ss =0v) symbol parameter min typ max unit t cycle enable cycle time 600 - - ns t eh enable pulse width 290 - - ns t as address setup time 5 - - ns t ds data setup time - - 290 ns t dh data hold time 10 - - ns t ah address hold time 20 - - ns figure 4. timing characteristics (read cycle)
motorola 3C322 mc141803 d/c (data / command) this input pin let the driver distinguish the input at d0-d7 is data or command. input high for data while input low for command. cs (clk) (chip select / input clock) this pin is normal low clock input. data on d0-d7 is latched at the falling edge of cs . res (reset) an active low pulse to this pin reset the internal status of the driver (same as power on reset). the minimum pulse width is 10 m s. ce (chip enable) high input to this pin to enable the control pins on the driver. d0-d7 this bi-directional bus is used for data / command transferring. r/w (read/write) this is an input pin. to read the display data ram or the internal status (busy / idle), pull this pin high. the r/w input low indicates a write operation to the display data ram or to the internal setup regis- ters. osc1 (oscillator input) for internal oscillator mode, this is an input for the internal low power rc oscillator circuit. in this mode, an external resistor of cer- tain value is placed between the osc1 and osc2 pins for a range of internal operating frequencies (refer to figure 1). for external oscilla- tor mode, osc1 should be left open. osc2 (oscillator output / external oscillator input) this is an output for the internal low power rc oscillator circuit. for external oscillator mode, osc2 will be an input pin for external clock and no external resistor is needed. vll6 - vll2 group of voltage level pins for driving the lcd panel. they can either be connected to external driving circuit for external bias supply or connected internally to built-in divider circuit. for internal voltage divider enabled, a 0.1 m f capacitor to av ss is required on each pin. dum1 and dum2 if internal voltage divider is enabled with 1/7 bias selected, a capacitor to av ss is required on each pin. otherwise, pull these two pin to av ss c1n and c1p if internal dc/dc converter is enabled, a capacitor is required to connect these two pins. c2n and c2p if internal tripler is enabled, a capacitor is required between these two pins. otherwise, leave these pin open. c+ and c- if internal divider circuit is enabled, a capacitor is required to con- nect between these two pins. vr and vf this is a feedback path for the gain control (external contrast con- trol) of vll1 to vll6. for adjusting the lcd driving voltage, it requires a feedback resistor placed between vr and vf, a gain con- trol resistor placed between vf and avss, a 10 m f capacitor placed between vr and avss. (refer to the application circuit) com0-com32 (row drivers) these pins provide the row driving signal to lcd panel. com0- com31 are used in 32 mux configuration. com0-com15 are used in 16 mux and no row remap configuration while com16-com31 are used in 16 mux with row remap configuration. com32 is used to drive the non-static icons in 33 mux. they output 0v during display off. (note : the ic facilitates two com32 pins, which output same signal, for the lcd panel layout flexibility.) seg0-seg119 (column drivers) these 120 pins provide lcd column driving signal to lcd panel. they output 0v during display off. bp (annunciator backplane) this pin combines with annun0-annun3 pins to form annunciator driving part. when the annunciator circuit is enabled, it will output square wave of f annn hz. it outputs low when oscillator is disabled. annun0 - annun3 (annunciator frontplanes) these pins are four independent annunciator driving outputs. the enabled annunciator outputs from its corresponding pin a f annn hz square wave which is 180 degrees out of phase with bp. disabled annunciator output from its corresponding pin an square wave in- phase with bp. when oscillator is disabled, all these pins output 0v. avdd and avss avdd is the positive supply to the noise sensitive circuitry in lcd driver and should be at same level as dvdd. avss is ground. vcc for using the internal dc/dc converter, a 0.1 m f capacitor from this pin to avss is required. it can also be an external bias input pin if internal dc/dc converter is not used. positive power is supplied to the lcd driving level selector and hv buffer cell with this pin. nor- mally, this pin is not intended to be a power supply to other compo- nent. dvdd and dvss power is supplied to the digital control circuit and other circuitry in lcd bias voltage generator of the driver using these two pins. dvdd is power and dvss is ground. pin descriptions
mc141803 3C323 motorola operation of liquid crystal display driver description of block diagram module command decoder and command interface this module determines whether the input data is interpreted as data or command. data is directed to this module based upon the input of the d/c pin. if d/c high, data is written to graphic display data ram (gddram). d/c low indicates that the input at d0-d7 is interpreted as a command. ce is the master chip selection signal. a high input enable the input lines ready to sample signals. reset is of same function as power on reset (por). once res received the reset pulse, all internal circuitry will back to its initial status. refer to command description section for more information. mpu parallel interface the parallel interface consists of 8 bi-directional data lines (d0- d7), r/w, and the cs. the r/w input high indicates a read opera- tion from the graphic display data ram (gddram). r/w input low indicates a write to display data ram or internal command regis- ters depending on the status of d/c input. the cs input serves as data latch signal (clock). refer to ac operation conditions and char- acteristics section for parallel interface timing description. graphic display data ram (gddram) the gddram is a bit mapped static ram holding the bit pattern to be displayed. the size of the ram is determined by number of row times the number of column (120x33 = 3960 bits). figure 5 is a description of the gddram address map. for mechanical flexibility, re-mapping on both segment and common outputs are provided. figure 5. graphic display data ram (gddram) address map column address 00h (or column address 77h) column address 77h (or column address 00h) page 1 page 2 page 3 page 4 lsb msb lsb msb lsb msb lsb msb com0 (com31) com31 (com0) seg119 row 0 row 31 note : the configuration in parentheses represents the remapping of row and columns seg0 lsb row 32 com32 page 5
motorola 3C324 mc141803 display timing generator this module is an on chip low power rc oscillator circuitry (figure 6). the oscillator frequency can be selected in the range of 15 khz to 50 khz by external resistor. one can enable the circuitry by soft- ware command. for external clock provided, feed the clock to osc2 and leave osc1 open. annunciator control circuit the lcd waveform of the 4 annunciators and bp are generated by this module. the 4 independent annunciators are enabled by software command. annunciator is also controlled by oscillator circuit too. annunciator output waveform shown in figure 7. figure 6. oscillator circuitry oscillation circuit enable2 osc1 osc2 feedback for internal oscillator for external clk input oscillator enable mc141803 external component buffer enable1 enable internal oscillator selected lcd driving voltage generator this module generates the lcd voltage needed for display output. it takes a single supply input and generate necessary bias voltages. it consists of : 1. voltage doubler and voltage tripler to generate the vcc voltage. either doubler or tripler can be enabled. 2. voltage regulator feedback gain control for initial lcd voltage. it can also be used with external contrast control. 3. voltage divider divide the lcd display voltage (v ll2 -v ll6 ) from the regulator out- put. this is a low power consumption circuit which can save the most display current compare with traditional resistor ladder method. 3. bias ratio selection circuitry software control of 1/5 and 1/7 bias ratio to match the characteris- tic of lcd panel. 4. self adjust temperature compensation circuitry provide 4 different compensation grade selections to satisfy the various liquid crystal temperature grades. the grading can be selected by software control. 5. contrast control block software control of 16 voltage levels of lcd voltage. 6. external contrast control by adjusting the gain control resistors connected externally, the contrast can be varied. refer to the application circuit for details. all blocks can be individually turned off if external voltage genera- tor is employed. 33 bit latch / 120 bit latch a 153 bit long register which carry the display signal information. first 33 bits are common driving signals and other 120 bits are seg- ment driving signals. data will be input to the hv-buffer cell for bumping up to the required level. level selector level selector is a control of the display synchronization. display voltage can be separated into two sets and used with different cycles. synchronization is important since it selects the required lcd voltage level to the hv buffer cell for output signal voltage pump. hv buffer cell (level shifter) hv buffer cell works as a level shift-er which translates the low voltage output signal to the required driving voltage. the output is shifted out with an internal frm clock which comes from the display timing generator. the voltage levels are given by the level selector which is synchronized with the internal m signal. lcd panel driving waveform the following is an example of how the common and segment drivers may be connected to a lcd panel. the waveforms shown in figure 7a, 7b and 7c illustrate the desired multiplex scheme. com1 com2 com3 com4 com5 com6 com7 seg1 seg2 seg3 seg4 com0 seg0 figure 7a. lcd display example 0
mc141803 3C325 motorola figure 7b. lcd driving signal from mc141803 1234 1234 vll6 vll5 vll4 vll3 vll2 vll1 -vll2 -vll3 -vll4 -vll5 -vll6 vll6 vll5 vll4 vll3 vll2 vll1 -vll2 -vll3 -vll4 -vll5 -vll6 seg0-com0 off pixel seg0-com1 on pixel time slot 1234 1234 vll6 vll5 vll4 vll3 vll2 vll1 vll6 vll5 vll4 vll3 vll2 vll1 vll6 vll5 vll4 vll3 vll2 vll1 vll6 vll5 vll4 vll3 vll2 vll1 com0 com1 seg0 seg1 time slot figure 7c. effective lcd waveform on lcd pixel
motorola 3C326 mc141803 command description set display on/off (display mode / stand-by mode) the display on command turns the lcd common and segment outputs on and has no effect to the annunciator output. this com- mand causes the conversion of data in gddram to necessary waveforms on the common and segment driving outputs. the on- chip bias generator is also turned on by this command. (note : oscil- lator on command should be sent before display on is selected) the display off command turns the display off and the states of the lcd driver are as follow during display off : 1. the common and segment outputs are fixed at v ll1 (v ss ). 2. the bias voltage generator is turned off. 3. the ram and content of all registers are retained. 4. ic will accept new commands and data. the status of the annunciators and oscillator are not affected by display off command. set gddram column address this command positions the address pointer on a column location. the address can be set to location 00h-77h (120 columns). the col- umn address will be increased by one automatically after a read or write operation. refer to address increment table and command set gddram page address. set gddram page address this command positions the row address to 1 of 5 possible posi- tions in gddram. refer to figure 5. master clear gddram this command is to clear the 480 byte gddram by setting the ram data to zero. issue this command followed by a dummy write command. the ram for icon line will not be affected by this com- mand. master clear icons this command is used to clear the data in page 5 of gddram which stores the icon line data. before using this command, set the page address to page 5 by the command set gddram page address. a dummy write data is also needed after this master clear icons command to make the clear icon action effective. set display with icon line if 1/32 mux selected, use this command change to 1/33 mux for using the icon line. this command can also change icon display mode to normal display mode (1/32 or 1/33 mux). set icon display mode this command force the output to the icon display mode. display on row 0 to row 31 will be disabled. set icon line / annunciator contrast level the contrast of the icon line and annunciators in icon mode can be set by this command. there are four levels to select from. set vertical scroll value this command is used to scroll the screen vertically with scroll value 0 to 31. with scroll value equals to 0, row 0 of gddram is mapped to com0 and row 1 through row 31 are mapped to com1 through com31 respectively. with scroll value equal to 1, row 1 of gddram is mapped to com0, then row 2 through row 31 will be mapped to com1 through com30 respectively and row 0 will be mapped to com31. com32 is not affected by this command. save / restore gddram column address with bit option = 1 in this command, the save / restore column address command saves a copy of the column address of gddram. with a bit option = 0, this command restores the copy obtained from the previous execution of saving column address. this instruction is very useful for writing full graphics characters that are larger than 8 pixels vertically. set column mapping this instruction selects the mapping of gddram to segment driv- ers for mechanical flexibility. there are 2 mappings to select: 1. column 0 - column 119 of gddram mapped to seg0-seg119 respectively; 2. column 0 - column 119 of gddram mapped to seg119-seg0 respectively. com32 will not be affected by this command. detailed information please refer to section display output description. set row mapping this instruction selects the mapping of gddram to common drivers for mechanical flexibility. there are 2 selected mappings: 1. row 0 - row 31 of gddram to com0 - com31 respectively; 2. row 0 - row 31 of gddram to com31 - com0 respectively. com32 will not be affected by this command. see section display output description for related information. set annunciator control signals this command is used to control the active states of the 4 stand alone annunciator drivers. set oscillator disable / enable this command is used to either disable or enable the oscillator. for using internal or external oscillator, this command should be exe- cuted. the setting for this command is not affected by command set display on/off and set annunciator control signal. see command set internal / external oscillator for more information set internal / external oscillator this command is used to select either internal or external oscilla- tor. when internal oscillator is selected, feedback resistor between osc1 and osc2 is needed. for external oscillation circuit, feed clock input signal to osc2 and leave osc1 open. set clock frequency use this command to choose from two different oscillation fre- quency (50khz or 38.4khz) to get the 60 hz frame frequency. with frequency high, 50 khz clock frequency is preferred. 38.4khz clock frequency (low frequency) enable for power saving purpose. set dc/dc converter on/off use this command selects the internal dc/dc converter to gener- ate the v cc from av dd . disable the internal dc/dc converter if external vcc is provided. set voltage doubler / tripler use this command to choose doubler or tripler when the internal dc/dc converter is enabled. set internal regulator on/off choose bit option 0 to disable the internal regulator. choose bit option 1 to enable internal regulator which consists of the internal contrast control and temperature compensation circuits.
mc141803 3C327 motorola set internal voltage divider on/off if the internal voltage divider is disabled, external bias can be used for v ll6 to v ll2. if the internal voltage divider is enabled, the internal circuit will automatically select the correct bias level accord- ing to the number of multiplex. refer to command bias ratio select. set duty cycle this command is to select 16 mux or 32 mux display. when 16 mux is enabled, the unused 16 common outputs will be swinging between vll2 and vll5 for dummy scan purpose and doubler will be used. set bias ratio this command sets the 1/5 bias or 1/7 bias for the divider output. the selection should match the characteristic of lcd panel. set internal contrast control on/off this command is used to turn on or off the intrernal control of delta voltage of the bias voltages. with bit option = 1, the software selec- tion for delta bias voltage control is enabled. with bit option = 0, inter- nal contrast control is disabled. increase / decrease contrast level if the internal contrast control is enabled, this command is used to increase or decrease the contrast level within the 16 contrast levels. the contrast level starts from lowest value after por. set contrast level this command is to select one of the 16 contrast levels when inter- nal contrast control circuitry is in use. read contrast value this command allows the user to read the current contrast level value. with r/w input high (read), d/c input low (command) and d7 d6 d5 d4 are equal to 0 0 0 1, the value of the internal contrast value can be read on d0-d3 at the falling edge of cs. set temperature coefficient this command can select 4 different lcd driving voltage tempera- ture coefficients to match various liquid crystal temperature grades. those temperature coefficients are specified in electrical character- istics tables. set i dd reduction mode on/off by using this command to reduce the display clock frequency by half. use in icon mode to reduce stand-by current.
motorola 3C328 mc141803 command table bit pattern command comment 00000x 2 x 1 x 0 set gddram page address set gddram page address using x 2 x 1 x 0 as address bits. x 2 x 1 x 0 =000 : page 1 (por) x 2 x 1 x 0 =001 : page 2 x 2 x 1 x 0 =010 : page 3 x 2 x 1 x 0 =011 : page 4 x 2 x 1 x 0 =100 : page 5 000011x 1 x 0 set icon line / annunciator contrast level set one of the 4 available values to the icon and annunciator con- trast, using x 1 x 0 as data bits. x 1 x 0 =00 (von = 0.87v dd ) x 1 x 0 =01 (von = 0.71v dd ) x 1 x 0 =10 (von = 0.61v dd ) por x 1 x 0 =11 (von = 0.55v dd ) 0001x 3 x 2 x 1 x 0 set contrast level set one of the 16 available values to the internal contrast register, using x 3 x 2 x 1 x 0 as data bits. the contrast register is reset to 0000 during por. 0001x 3 x 2 x 1 x 0 read contrast value with d/c pin input low, r/w pin input high, and d7 d6 d5 d4 pins equal to 0001 at the rising edge of cs , the value of the internal contrast register will be latched out at d3 d2 d1 d0 pins, i.e. x 3 x 2 x 1 x 0 , at the rising edge of cs . 0010000x 0 set voltage doubler / tripler x 0 =0: select voltage tripler (por) x 0 =1: select voltage doubler 0010001x 0 set column mapping x 0 =0 : col0 to seg0 (por) x 0 =1 : col0 to seg119 0010010x 0 set row mapping x 0 =0 : row0 to com0 (por) x 0 =1: row0 to com31 0010011x 0 reserved 0010100x 0 set display on/off x 0 =0: display off (por) x 0 =1: display on 0010101x 0 set dc/dc converter on/off x 0 =0: dc/dc converter off (por) x 0 =1: dc/dc converter on 0010110x 0 set internal regulator on/off x 0 =0: internal regulator off (por) x 0 =1: internal regulator on when the application employs external contrast control, the inter- nal contrast control, temperature compensation and the regulator must be enabled. 0010111x 0 set internal voltage divider on/off x 0 =0: internal voltage divider off (por) x 0 =1: internal voltage divider on when an external bias network is preferred, the voltage divider should be disabled. 0011000x 0 set internal contrast control on/off x 0 =0: internal contrast control off (por) x 0 =1: internal contrast control on internal contrast circuits can be disabled if external contrast cir- cuits is preferred. 0011001x 0 set clock frequency x 0 =0 : low frequency (38.4khz) (por) x 0 =1 : high frequency (50khz) 0011010x 0 save/restore gddram column address x 0 =0 : restore address x 0 =1 : save address 00110110 master clear gddram master clear gddram page 1 to 4 00110111 master clear icons master clear of gddram page 5. gddram page 5 should be selected and dummy write is required 0011100x 0 set bias ratio x 0 =0: set 1/7 bias (por) x 0 =1: set 1/5 bias 0011101x 0 reserved. x 0 =0: normal operation (por) x 0 =1: test mode (note: make sure to set x 0 =0 during application)
mc141803 3C329 motorola bit pattern command comment 0011110x 0 set display with icon line x 0 =0: set display mode without icon line (por) x 0 =1: set display mode with icon line 00111110 set icon display mode power saving icon display mode, com0 to com31 will be disabled 010x 4 x 3 x 2 x 1 x 0 set vertical scroll value use x 4 x 3 x 2 x 1 x 0 as number of lines to scroll. scroll value = 0 upon por 01100a 1 a 0 x 0 set annunciator control signals a 1 a 0 =00: select annunciator 1 (por) a 1 a 0 =01: select annunciator 2 a 1 a 0 =10: select annunciator 3 a 1 a 0 =11: select annunciator 4 x 0 =0: turn selected annunciator off (por) x 0 =1: turn selected annunciator on 0110100x 0 set duty cycle x 0 =0: 1/32 duty and tripler enabled (por) x 0 =1: 1/16 duty and doubler enabled 0110101x 0 set i dd reduction mode x 0 =0: normal mode x 0 =1: i dd reduction mode 011011x 1 x 0 set temperature coef?cient x 1 x 0 =00 : 0.00% (por) x 1 x 0 =01 : -0.18% x 1 x 0 =10 : -0.22% x 1 x 0 =11 : -0.35% 0111000x 0 increase / decrease contrast value x 0 =0: decrease by one level x 0 =1: increase by one level (note: increment/decrement wraps round among the 16 contrast levels. start at the lowest level when por. 0111001x 0 reserved 0111010x 0 reserved 0111011x 0 reserved x 0 =0: normal operation (por) x 0 =1: test mode select (note: make sure to set x 0 =0 during application) 0111100x 0 reserved 0111101x 0 set internal / external oscillator x 0 =0: internal oscillator (por) x 0 =1: external oscillator. internal oscillator circuit is automatically enabled if resistors are placed at osc1 and osc2. for external oscillator, simply feed clock in osc2. 0111110x 0 reserved 0111111x 0 set oscillator disable / enable x 0 =0: oscillator disable (por) x 0 =1: oscillator enable. this is the master control fro oscillator circuitry. this command should be issued after the external / internal oscillator com- mand. 1x 6 x 5 x 4 x 3 x 2 x 1 x 0 set gddram column address set gddram column address. use x 6 x 5 x 4 x 3 x 2 x 1 x 0 as address bits. data read / write to read data from the gddram, input high to r/w pin and d/c pin. data is valid at the falling edge of cs . and the gddram column address pointer will be increased by one automatically. to write data to the gddram, input low to r/w pin and high to d/c pin. data is latched at the falling edge of cs . and the gddram column address pointer will be increased by one automatically. no auto address pointer increment will be performed for the dummy write data after master clear gddram. (refer to the commands required for r/w actions on ram table)
motorola 3C330 mc141803 address increment table (automatic) address increment is done automatically data read write. the column address pointer of gddram *3 is affected. remarks : *1. refer to the command read contrast value. *2. if write data is issued after command clear ram, address increase is not applied. *3. column address will be wrapped round when overflow. d/c r/w comment address increment remarks 0 0 write command no 0 1 read command no *1 1 0 write data yes *2 1 1 read data yes power up sequence (commands required) command required por status remarks set clock frequency set oscillator enable set annunciator control signals set duty cycle set bias ratio set interna dc/dc converter on set internal regulator on set temperature coef?cient set internal contrast control on increase contrast level set internal voltage divider on set segment mapping set common mapping set vertical scroll value set display on low disable annunciator all off 1/32 duty 1/7 bias off off tc=0% off contrast level = 0 off seg. 0 = col. 0 com. 0 = row 0 scroll value = 0 off *1 *1 *1 *1 *1 *1 *1 *1, *3 *1, *3 *1, *2, *3 *1 commands required for display mode setup other related command with display mode : set duty cycle, set column mapping, set row mapping, set vertical scroll value. commands related to internal dc/dc converter : set oscillator disable / enable, set internal regulator on/off, set duty cycle, set temperature coefficient, set internal contr ast control on/ off, increase / decrease contrast level, set internal voltage divider on/off, set bias ratio, set display on/off, set internal / external oscilla- tor, set contrast level, set voltage doubler / tripler, set 33 mux display mode, set icon display mode * no need to resend the command again if it is set previously . display mode commands required display mode set external / internal oscillator, set oscillator enable, set display on. (0111101x 0 )* (01111111)* (00101001)* annunciator display set external / internal oscillator, set oscillator enable, set annunciator control signal. (0111101x 0 )* (01111111)* (01100a 1 a 0 x 0 )* standby mode 1. set display off, set oscillator disable. (00101000)* (01111110)* standby mode 2. set external oscillator, set annunciator control signal, set display off, set oscillator enable. (01111011)* (01100a 1 a 0 x 0 )* (00101000)* (01111111)* standby mode 3. set internal oscillator, set annunciator control signal, set display off, set oscillator enable. (01111010)* (01100a 1 a 0 x 0 )* (00101000)* (01111111)* remarks : *1 -- required only if desired status differ from por. *2 -- effective only if internal contrast control is enabled. *3 -- effective only if regulator is enabled.
mc141803 3C331 motorola commands required for r/w actions on ram * no need to resend the command again if it is set previously . r/w actions on rams commands required read/write data from/to gddram. set gddram page address set gddram column address read/write data (000x 4 x 3 x 2 x 1 x 0 )* (1x 6 x 5 x 4 x 3 x 2 x 1 x 0 )* (x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 ) save/restore gddram column address. save/restore gddram column address. (0011010x 0 ) increase gddram address by one dummy read data (x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 ) master clear gddram master clear gddram dummy write data (00110110) (x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 ) display output description this is an example of output pattern on the lcd panel. figure 8b and 8c are data map of gddram and the output pattern on the lc d display with different command enabled. com0 com31 seg0 seg119 com32 content of gddram page 1 upper nibble lower nibble 5a5a5a5a5a---------5a5a5a5a5a 5a5a5a5a5a---------5a5a5a5a5a page 2 upper nibble lower nibble 33cc33cc33---------cc33cc33cc 33cc33cc33---------cc33cc33cc page 3 upper nibble lower nibble 0000ffff00---------ff0000ffff ffff0000ff---------00ffff0000 page 4 upper nibble lower nibble ffffffff00---------ff00000000 ffffffff00---------ff00000000 page 5 upper nibble lower nibble 0000000000---------0000000000 0001110000---------0000111000 column remap enable row re-map disable column remap disable row re-map disable column remap disable row re-map enable column remap disable row re-map disable scroll value = 31 figure 8c. examples of lcd display with different command enabled figure 8b figure 8a
motorola 3C332 mc141803 copper side MC141803T tab package dimension (1 of 2) 98asl10017a issue 0 do not scale this drawing
mc141803 3C333 motorola MC141803T tab package dimension (2 of 2) 98asl10017a issue 0 do not scale this drawing
motorola 3C334 mc141803 32/33 mux display with analog circuitry enabled, tripler enabled and 1/7 bias application circuit remark : 1. vr and vf can be left open for regulator disable. 2. cs pin low at standby mode. cmos mpu/ mcu with parallel interface eprom to lcd panel vll2 vll3 dum2 dum1 vll4 vll5 vll6 vcc com0 to com32 seg0 to seg119 annun 0-3 and bp osc2 osc1 c+ c- vf vr c2p c2n c1p c1n res d/c cs ce r/w d0~d7 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 1m w 200k w 760k w 560pf 0.1 m f 0.1 m f 0.1 m f 4.7 m f mc141803 ram dvss dvdd avdd avss 0.1 m f 0.1 m f dv dd av dd
mc141803 3C335 motorola 16 mux display with analog circuitry enabled, tripler disabled and 1/5 bias application circuit cmos mpu/ mcu with parallel interface eprom to lcd panel vll2 vll3 dum2 dum1 vll4 vll5 vll6 vcc com0 to com32 seg0 to seg119 annun 0-3 and bp osc2 osc1 c+ c- vf vr c2p c2n c1p c1n res d/c cs ce r/w d0~d7 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 200k w 760k w 560pf 0.1 m f 0.1 m f 4.7 m f ram external clock remark : 1. vr and vf can be left open for regulator disable. 2. cs pin low at standby mode. dvss dvdd avdd avss 0.1 m f 0.1 m f dv dd av dd mc141803
motorola 3C336 mc141803 16/32/33 mux display with analog circuitry disabled to lcd panel vll2 vll3 dum2 dum1 vll4 vll5 vll6 vcc com0 to com32 seg0 to seg119 annun 0-3 and bp osc1 c+ c- vf vr c2p c2n c1p c1n cmos mpu/ mcu with parallel interface eprom res d/c cs ce r/w d0~d7 ram osc2 external clock remark : 1. vr and vf can be left open for regulator disable. 2. cs pin low at standby mode. application circuit dvss dvdd avdd avss 0.1 m f 0.1 m f dv dd av dd v cc mc141803

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